Operating system based dram and flash management

ABSTRACT

A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of application Ser. No. 12/059,784filed Mar. 31, 2008, the entire contents of which is hereby incorporatedby reference.

TECHNICAL FIELD

The subject innovation relates generally to memory systems and inparticular to systems and methods that employ FLASH memory technology inlieu of conventional DRAM memory subsystems.

BACKGROUND

A wide variety of memory devices can be used to maintain and store dataand instructions for various computers and similar systems. Inparticular, FLASH memory is a type of electronic memory media that canbe rewritten and that can retain content without consumption of power.Unlike dynamic random access memory (DRAM) devices and static randommemory (SRAM) devices in which a single byte can be erased, FLASH memorydevices are typically erased in fixed multi-bit blocks or sectors. FLASHmemory technology can include NOR FLASH memory and/or NAND FLASH memory,for example. FLASH memory devices typically are less expensive anddenser as compared to many other memory devices, meaning that FLASHmemory devices can store more data per unit area.

FLASH memory has become popular, at least in part, because it combinesthe advantages of the high density and low cost of EPROM with theelectrical erasability of EEPROM. FLASH memory is nonvolatile; it can berewritten and can hold its content without power. It can be used in manyportable electronic products, such as cell phones, portable computers,voice recorders, thumbnail drives and the like, as well as in manylarger electronic systems, such as cars, planes, industrial controlsystems, etc. The fact that FLASH memory can be rewritten, as well asits retention of data without a power source, small size, and lightweight, have all combined to make FLASH memory devices useful andpopular means for transporting and maintaining data.

Typically, when data is stored in a physical location (e.g., physicalblock address (PBA)) in a memory device, a system block address (LBA)can be associated with the data to facilitate retrieval of the data fromthe memory by a host. An address translation table can be used to storethe translations of LBAs to the PBAs. When the host requests data fromor desires to write data to a particular LBA, the address translationtable can be accessed to determine the PBA that is associated with theLBA. The LBA associated with the data can remain the same even if thePBA where the data is stored changes. For example, a block of memorycontaining the PBA can have antiquated data in other memory locations inthe block. The block of memory can be erased to reclaim the block, andvalid data stored in the block, including the data in the PBA, can bemoved to new physical locations in the memory. While the PBA of the datais changed, the LBA can remain the same. The address translation tablecan be updated to associate the new PBA with the LBA.

In conventional computing systems, DRAM technology has typically beenemployed to operate the dynamic memory of the computer in order for anapplication to operate at high speeds. Slower speed memories such ashard drives and FLASH technology have been utilized for non-volatilelong term storage requirements. As previously noted, FLASH provideslower power consumption with higher density capability per package sizethan DRAM. It would be desirable if some of the advantages of FLASHtechnology could be exploited to support many of the applications thatare currently running with DRAM technology. Unfortunately, therecurrently are bandwidth issues with FLASH that would not allow for adirect substitution with existing DRAM applications.

SUMMARY

The following presents a simplified summary of the innovation in orderto provide a basic understanding of some aspects described herein. Thissummary is not an extensive overview of the disclosed subject matter. Itis intended to neither identify key or critical elements of thedisclosed subject matter nor delineate the scope of the subjectinnovation. Its sole purpose is to present some concepts of thedisclosed subject matter in a simplified form as a prelude to the moredetailed description that is presented later.

Operating system kernel enhancements are provided to enable FLASH memorytechnologies to be utilized for existing DRAM applications in computermemory subsystems. In one aspect, basic components of a memorymanagement system are analyzed and modified to enable recognition of aFLASH architecture as the main memory component of the system yet alsoprocess memory operations in view of a DRAM buffer that allows thesystem to account for timing/programming nuances of FLASH operations.Such nuances include longer write times to FLASH memory thanconventional DRAM memory as well as defined paging requirements whereentire segments of FLASH are updated as opposed to a single byte or wordof memory as in conventional DRAM systems.

In order to account for FLASH characteristics and the segmented natureof main memory between FLASH space and DRAM buffer space, variouscomponents are provided to manage access to the respective spaces. Inone aspect, when data is fetched from main memory, a determination ismade as to whether or not read or write access is detected. Suchdetermination can be triggered off of a page fault mechanism (or otherevent) associated with the kernel. If a read is attempted, FLASH can beallocated for the read yet marked to indicate that a previous allocationhas occurred. If a write is later detected, a DRAM buffer page can beallocated to account for temporary latencies of writing to FLASH and toallow a de-mapping of the FLASH. A follow-on copy instruction or otherfunction can be employed to synchronize what has been written to DRAMand the previously allocated FLASH memory. In this manner, FLASH can beupdated during background operations while mitigating program delaysassociated with latency or other sector management.

In yet another aspect, a page buffer can be sized to account forbuffering at least one page of FLASH memory during page-in operationsfrom permanent storage devices. Typically, the amount buffered willallow program operations to continue normally while the FLASH is updatedduring background operations. For higher throughput applications wherememory may be accessed at a higher rate, the buffer can be sized forgreater capacity to allow program operations to continue and not bestalled by respective writes to the FLASH. In still yet another aspect,additional memory lists can be created, where one of the listsfacilitates mapping and de-mapping of FLASH memory and the other listsfacilitates mapping and de-mapping of the associated DRAM buffer area.It is noted that FLASH and DRAM buffer management can occur via hardwarecomponents such as an application integrated circuit, via softwarecomponents such as the kernel modifications described herein, and canalso occur as a combination of hardware and/or software solutions.

The following description and the annexed drawings set forth in detailcertain illustrative aspects of the disclosed subject matter. Theseaspects are indicative, however, of but a few of the various ways inwhich the principles of the innovation may be employed and the disclosedsubject matter is intended to include all such aspects and theirequivalents. Other advantages and distinctive features of the disclosedsubject matter will become apparent from the following detaileddescription of the innovation when considered in conjunction with thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of a FLASH memory kernel architectureemployed for random access memory applications.

FIG. 2 depicts a block diagram of a FLASH and DRAM allocation system.

FIG. 3 illustrates a block diagram of a system that employs alternativelists to manage mapping operations between FLASH and DRAM.

FIG. 4 is a block diagram depicting a kernel architecture adapted for aDRAM page buffer.

FIGS. 5-7 illustrate example process methodologies for managing FLASHsubsystems that employ DRAM buffers to facilitate FLASH interfacerequirements.

FIG. 8 illustrates a block diagram of a FLASH memory architectureemployed for random access memory applications.

FIG. 9 depicts a block diagram of a wear leveling system for FLASHmemory.

FIG. 10 is a block diagram depicting DRAM sizing and FLASH writeconsiderations.

FIG. 11 illustrates a block diagram of a system that partially allocatescontents from FLASH to mitigate system bus activity.

FIG. 12 illustrates an example of an electronic device that can beassociated with a memory.

DETAILED DESCRIPTION

Systems and/or methods are presented that facilitate usage of FLASHmemory technologies in place of conventional DRAM subsystems. In oneaspect, a memory system is provided. The system includes an operatingsystem kernel that regulates read and write access to one or more FLASHmemory devices that are employed for random access memory applications.A buffer component operates in conjunction with the kernel to regulateread and write access to the one or more FLASH devices. Variouscomponents are provided with the kernel to support a FLASH main memory,where DRAM is employed to account for programming nuances of the FLASH.

Referring initially to FIG. 1, a system 100 illustrates a FLASH memorykernel architecture employed for random access memory applications. Thesystem 100 includes an operating system 110 with various components of akernel such as a virtual memory management component 114 (also referredto as VMM 114) that controls how program memory is utilized by one ormore programs executing in accordance with the operating system. Asshown, the operating system 110 and VMM 114 generate virtual andphysical addresses 120 that are employed by one or more processors 130to read and write data with a FLASH memory 140 and a DRAM buffer 150. Ingeneral, the DRAM buffer is provided to accommodate architecturalnuances associated with the FLASH memory 140. Such nuances includeslower write times for data to the FLASH 140 and latency associated withhaving to update entire sectors of the FLASH 140 instead of individualaddresses as in conventional systems that employ DRAM entirely for mainmemory. Thus, various components are added to the operating system 114and associated kernel to map virtual addresses and physical addresses120 in view of the segmented memory architecture shown where the FLASHmemory 140 is employed as the main memory and the DRAM buffer 150 isemployed to account for latencies and to mitigate program delays as willbe described in more detail below.

In general, the system 100 provides an operating system 110 that allowsboth DRAM 150 and FLASH memory 140 devices in the physical main memorypool and can manage the combined memory pool as memory pages withouthaving to navigate through a file system layer. In order to create anoperating system 110 capable of accommodating both DRAM 150 and FLASHmemory 140 as the physical main memory there are various components thatare provided that facilitate Kernel execution remains as efficient as itwas in a full DRAM system. Thus, the Virtual Memory Management 114sub-system is modified for the respective FLASH memory 140characteristics and can manage the combined page resources suitably.Other components of the operating system can include:

a. A component 160 that keeps track of program/erase cycles of devicegroups in which program/erase cycles are still under way.

b. A component 164 that can process DRAM pages and the FLASH pagesthrough their respective life cycles.

c. A component 170 which can free up both DRAM and FLASH pages whenavailable memory of either type is low.

d. A component 174 which allocates the appropriate type of pages basedon:

i. access types, Read or Write;

ii. which type of page faults, major, minor of protection;

iii. Whether or not it hits and existing mapped page;

Other aspects include providing a component 180 which can identify anddistinguish between a DRAM DIMM (dual inline memory module) and a FLASHDIMM to determine the total capacity of both types of memories duringsystem boot-up. One type of DIMM resides on a DDR memory channel thatcan buffer a few pages of data and provide instant data forwarding afterthe data is written into the buffer 150. Also, the allocation component174 can seamlessly allocate a DRAM page for a Write reference that hitson a FLASH page. Before proceeding, a few of the following terms aredescribed:

Kernel: Center Piece of an Operating System 110.

Process: An executable form of a program.

Virtual Memory Management Sub-system (VM): Presents a simple memoryprogramming model to applications and provides a programming model witha larger memory size than that of available physical main memory toenable use of slower but larger secondary storage.

Address Space of a Process: Is the range of memory addresses that arepresented to the process as its environment; as a process progresses,some addresses are mapped to physical memory, whereas some are not.FIGS. 2-4 will now described systems and components that support thedual memory type architecture depicted in FIG. 1 whereas FIGS. 5-7depict associated methods.

Referring now to FIG. 2, a FLASH and DRAM allocation system 200 isillustrated. In general and as noted previously, FLASH memory has alimitation with regard to accepting content updates, both in bandwidthand in granularity when compared to a DRAM device. The systems describedbelow with respect to FIGS. 8-11 employ DRAM devices as buffer to helpmitigate the Writes and employ an ASIC to manage the DRAM as well as theFLASH devices. The system 200 provides an operating system change whichutilize existing mechanisms, plus minimal new routines to manage ahybrid DRAM and FLASH memory subsystem without needing an controllerASIC. As shown, the system 200 includes a fetch page detection component210 that determines when a page is fetched from permanent storage. Thisinvokes read or write detection operations at 220. If a page read isdetected, FLASH memory is allocated and subsequently marked or tagged asallocated at 230. If a write is detected, DRAM is updated at 240 and asubsequent function is called to transfer buffered contents from theDRAM to the FLASH during background operations of the operating system.More detailed methodologies that are employed by the system 200 areillustrated and described with respect to FIGS. 5 and 6 below.

When an operating system initiates a process, a range of virtual addressis assigned to the process. A page table is also built. Read and Writeaccess will then refer to the table. If an entry is valid, properphysical address (PA) is obtained and access to main memory is made. Ifan entry is not valid, a page fault trap occurred and an operatingsystem page handler routine is invoked which moves the page from disk tothe main memory at 210. When the main memory is full and a new page fromdisk needs to be brought in, a page is selected based on replacementalgorithms and pushed back to the disk if dirty (modified during itstenure in the main memory). This activity is referred to as swapping.When a process is run and its working set changes, the process swapspages between memory and disk during the run when necessary. However,the indication of demands of the pages comes from both Read and Writeaccesses. In a hybrid DRAM/FLASH system described herein, where bothDRAM DIMMs and FLASH DIMMs exist, the Writes are directed to the DRAM at240 and Read from DRAM and FLASH.

In one specific example, a fork ( ) Linux routine which initiates achild process into a “copy-on-write” mode could be employed and isdescribed in more detail in FIG. 5. In the fork ( ) using“copy-on-write”, the child process has a new virtual address (VA) and anew page table. However, the new page table has entries pointing to allphysical pages the parent process points to. Thus, the entries aremarked “copy-on-write” protection. Upon a write access demand on a page,the “copy-on-write” protection flag will have the page fault handlerfetch a new physical page to process the write.

Upon system start up, a process will use page fault (or other mechanismat 210) to bring in the pages from the disk. When that process iscomplete, the fork ( ) is employed and relies on the child process totake all future Writes. Thus, new pages allocated by the page faulthandler due to the copy-on-write will bring in pages only from the DRAM.In other words, the DRAM will now hold the “write working set” and theoperating system should swap pages into disk (or potentially to FLASH)when necessary, similar to the typical ‘swapping” activity but only forthe write pages and only for the DRAM pages. For the read accesstriggered swapping, the operating system should perform the swappingsimilar to the traditional swapping but only for the read and only forthe FLASH.

When bringing data from the disk during page fault handling, theoperating system can employ DMA (direct memory access controller) whichis FLASH aware, i.e., understands the FLASH's program and erasemechanisms. An erase command is sent to the FLASH and then data chunkswhich corresponds to the maximum data chunk a FLASH can allow is used asthe DMA size. Multiples of this type of DMA is used to bring in a pagefrom disk to the FLASH. Among these DMA's, proper wait time is insertedby the operating system to ensure FLASH Memory program latency issatisfied. As noted above, more detailed flow diagrams are provided inFIGS. 5 and 6.

Referring to FIG. 3, a system that employs alternative lists to managemapping operations between FLASH and DRAM. In general, when a singletype of memory is employed, a single cache list and free list can beemployed to manage program memory requirements. The system 300 depicts adual-natured system where a virtual memory manager provides a mappingand memory type detector 320 and a cache and free list 330 for a FLASHmemory type. In addition, a separate path is maintained mapping andmemory type detector 340 and a cache and free list 350 for an associatedDRAM memory type.

In general, state of the art operating systems currently used by laptop,desktop and server computers manage main memory resource through asub-system called “Virtual Memory Management.” This subsystem assumesmain memory to consist of only DRAM type of devices which can handleDRAM type of access patterns. With the advance of FLASH memory and itslow power and non-volatility characteristics, there is a great benefitto add FLASH Memory devices to the main memory resource pool.Unfortunately, existing operating systems do not have a provision towork with FLASH memory without a file system and can not process thecharacteristics of the FLASH Memory devices occupying in the main memoryresource pool. The system 200 provides a resource management scheme inthe Virtual Memory Management subsystem which provides an operatingsystem the ability to manage DRAM and FLASH resources separately. Inaddition to the other systems described herein, this enables theadoption of FLASH memory devices into the desktop and server computersystems' main memory pool.

Generally, various approaches can achieve the dual memory typemanagement. One approach is to have separate cache list and free listfor the FLASH Memory pool at 330, besides having the existing cache listand free list for the DRAM pool at 350. Joint lists can work as well byadding identification for each element (page) of the link list such thata page allocation function can choose either DRAM or FLASH memory pagesas it attempts to locate an available page from the main memory poolduring handling of a page fault. With respect to the approach of havinga separate cache list and free list for the FLASH Memory, besides theexisting pair for the DRAM. Various components are described below:

(1) Pages in the DRAM pool and pages in the FLASH Memory pool will gothrough their own page life cycle.

(2) Page scanner scans all pages but frees the pages to their respectivelists. The flush daemon part of the page scanner will scan only the DRAMrelated list since the FLASH related list won't be “dirty.” Page scanneris triggered during either DRAM shortage or FLASH shortage.

(3) Three types of page faults: Major, Minor, protection;

a. Major page fault, Read page fault should trigger a page-in from themain storage (in most cases disks) to the FLASH Memory. All pagespaged-in in this manner can be marked “copy-on-write” protection (seeFIG. 2 description above). Write page fault should trigger a page-infrom the main storage to the DRAM.

b. Minor page fault, if the existing physical page is a DRAM page theminor page fault should trigger a regular “Attach” where the faultingprocess will establish a mapping to the existing physical page,regardless of Read or Write page faults. If the existing physical pageis a FLASH page, the Read minor page fault should trigger a regular“Attach” where the faulting process will establish a mapping to theexisting physical page. If it is a Write minor page fault, it should behandled as a protection page fault.

c. Protection page fault: Other than or in addition to usual protectionpage fault. When a write miss triggers a “copy-on-write” protection pagefault on a FLASH page, a new DRAM page is allocated for the write andexisting FLASH physical page is de-mapped.

(4) As a configurable option: Normally de-mapped DRAM page can stay inthe cache list and eventually free list. If a Write page fault hits thesame (vnode, offset) the page can be mapped again. While it is still inthe cache list, an option is to allocate the DRAM page directly upon aRead page fault hitting the (vnode, offset). Another option is to movepages as a background daemon from the DRAM cache list to the FLASH cachelist in anticipation of future Read page faults. It is noted that vnodeis a virtual node describing the beginning of a file location and offsetis an index into the respective file. The vnode and offset thus arespecified in a pair and employed to map or de-map physical and virtualaddresses within the confines for main memory which includes FLASH and aDRAM buffer.

(5) It is noted that care should be taken when paging-in from the mainstorage (most often a disk) to the FLASH main memory pool due to thelong Program/Erase cycle. A FLASH DIMM with page buffer and dataforwarding capability (described in FIG. 4) can be used to facilitateefficient DMA activities and provides immediately available page datafor the “de-waitlisted” processes right after DMA completion. However,even with the FLASH DIMM, the kernel may need to be aware of the pendingProgram/Erase cycles within the DIMM and FLASH devices to avoidoverrunning the page buffer within the DIMM. Utilizing the addressinterleaving controls within the memory controller and/or usingmechanisms built-in within the DIMM can help to spread out sequentialpages' page-in activities into multiple device groups instead ofconcentrating on a single device group and having to handle the page-inserially. A more detailed flow diagram is provided in FIG. 6 thatillustrates some of the concepts described with respect to the system300.

Referring to FIG. 4, a system 400 illustrates page bufferconsiderations. The system 400 includes a page-in component 410 thatprocesses memory writes 420 that are temporarily stored in a page buffer430. A memory manager 440 guides data into the page buffer 430 and alsois responsible for transferring buffer contents to FLASH 450 duringbackground operations of the operating system. During backgroundtransfers, data can be read from the page buffer 430 to mitigate programdelay.

Conventional FLASH memory with DDR (dynamic data ram) resolveselectrical and protocol difference between the DDR and a typical FLASHmemory. It enables FLASH memory devices or DIMM to sit on a DDR channel(bus). However, such memory does not change the inherent write bandwidthand latency limitation of a FLASH memory device. Therefore, a FLASHmemory with DDR interface continues to be hard to use. The system 400assumes an operating system which is aware of the existence of FLASHmemory devices in the main memory pool. It provides an efficient way forthe operating system to transition from page-in activity where allprocesses that use this page are wait-listed to allowing all processesthat were wait-listed to proceed without explicit wait counter withinthe DMA device driver and without having to have all processes that werewaiting on the page to wait for the complete Program and Erase cycle ofa FLASH memory.

When the execution of a program encounters a page fault, there exists nomapping between process's virtual address page being accessed and aphysical page in main memory. The kernel (core of the operating system)will find a free physical page in the main memory pool and bring in therequested data from the main storage which most frequently is in theform of a disk. This activity is called page-in. While page-in is inprogress, all processes that refer to this particular page arewait-listed until the page-in activity is complete. When a process is nolonger wait-listed for the page, it can proceed and perform a Read fromthat page. For a typical DRAM based DIMM, the DRAM device as soon as theDRAM engine completes the page write signals the kernel in order thatthe kernel can release the wait-listed processes. Unfortunately for theFLASH memory, the entire Program and Erase for a block (also referred toas a sector) is in tens of milliseconds. Without the Program and Erasebeing complete the incoming read will not be able to access the updateddata.

Instead of having a DRAM device driver or kernel core wait for theperiod of the entire Program and Erase cycles, the page buffer 430 isintroduced to temporarily hold a least one page of data so a typical DMAdriver can perform the write and signal the kernel as if it weretargeting a DRAM device. The kernel can then bring the waiting processesout for the wait-listed mode to match the performance of a typical DRAMbased application. This page buffer 430 is preferably SRAM (static RAM)but can be DRAM device or other devices, embedded or not, that canprovide fast write and read capability. The buffer 430 can also haveaddress match logic which compares the incoming address to decide if thedata return should be from the page buffer or from the actual FLASHdevice. The incoming address path goes straight to the underlying FLASHdevice to avoid losing precious latency. The address match logic canproduce a match or mismatch result which in turns will drive amultiplexer for the data return.

FIGS. 5-7 illustrate example process methodologies for managing FLASHsubsystems that employ DRAM buffers to facilitate FLASH interfacerequirements. While, for purposes of simplicity of explanation, theprocesses or methodologies are shown and described as a series or numberof acts, it is to be understood and appreciated that the subjectprocesses are not limited by the order of acts, as some acts may, inaccordance with the subject processes, occur in different orders and/orconcurrently with other acts from that shown and described herein. Forexample, those skilled in the art will understand and appreciate that amethodology could alternatively be represented as a series ofinterrelated states or events, such as in a state diagram. Moreover, notall illustrated acts may be required to implement a methodology inaccordance with the subject processes described herein.

Referring to FIG. 5, an example process 500 is illustrated that supportsthe system described in FIG. 2. At 510, a page fault is generated whenmemory is accessed from permanent storage device. The page faulttriggers a determination at 520 to determine if the operation is a writeor read sequence to the respective main program memory devices. If theoperation is a read at 520, the process proceeds to allocate a flashpage at 530 and marks or tags or flags the respective page as acopy-on-write page before proceeding with other program operations. Ifthe operation detected at 520 is a write, a DRAM page is allocated at540 and a FLASH page is de-mapped (e.g., vnode and offset pairsre-assigned). As shown a 540, a copy-on-write for example can beemployed to perform such DRAM allocation and de-mapping. The process 500will now be shown in the context of a larger operating system managementscheme in FIG. 6.

Referring to FIG. 6, a memory management process 600 is illustrated. At614, a system boot is performed. A boot prom loads base kernel code at616, creates kernel address spaces at 618, where the user then starts aprogram process at 620. The process at 620 generates a page fault at624, where a read or write determination is then performed at 626. If aprocess read is detected at 626, the process proceeds to 628 todetermine a fault type. If a minor fault is detected at 628, then attachread to the DRAM page at 630. If a major fault is detected at 628, thenallocate flash and mark as copy-on-right at 632. As shown, free memory634 is allocated between FLASH and DRAM at 636. If a protection fault isdetected at 628, existing operating system page protecting schemes canbe followed at 640.

Referring back to decision branch 626, the write decision branch isanalyzed. If a write is detected from 624, the type of fault is gainanalyzed at 644. If a protection fault is determined at 644, the processproceeds to 640 and follows existing schemes. If a major fault isdetected at 644, the process proceeds to 636 and allocates a DRAM page.If a minor fault is detected at 644, the process proceeds to 650. At650, a determination is made as to whether or not an existing page isalready in DRAM. If yes, a shared page determination is made at 654. Ifa page is shared at 654, an attachment is made at 656. If a shared pageis not found at 654, the process proceeds to 636 and allocates a DRAMpage. If an existing page is not in DRAM at 650, the process proceeds to660 and allocates a DRAM page while de-mapping a FLASH page. Acopy-on-write is then performed as previously described.

Referring briefly to FIG. 7, a dual memory list process is illustratedthat supports the system described in FIG. 3. In this aspect, a FLASHfree memory area is maintained at 710 and a DRAM free memory area iscreated at 720. Each of the respective areas 710 and 720 include a cachelist and free list portion for the respective FLASH and DRAM segments ofmemory. As shown, pages that are mapped to Virtual Address (VA) spaceand where a swap file system operation is performed at 730, a decisionis made 740 whether or not to direct updates to the FLASH area of 710 orDRAM area 720. Similarly, if pages are mapped to a VA and a file at 750,data is then routed at 760 to the respective areas 710 and 720 dependingon if it is designated for FLASH or DRAM. It is noted that a cache listcan be structured as a hashed list by (vnode, offset). Thus, it ispossible to combine the Flash cache list and the DRAM cache list.However, one would need to resolve the “tail” issue since when the freelist is depleted, the tail of the cache list is served as “Free Memory.”

Referring now to FIG. 8, a system 800 illustrates a FLASH memoryarchitecture that is employed to support random access computer memoryapplications. Before proceeding, it is noted that the systems describedbelow describe various hardware solutions for a dual memory architectureemploying FLASH and DRAM. It is to be appreciated that processing forthe dual memory nature can occur via hardware components, softwarecomponents, and/or a combination of hardware and software.

The system 800 includes a processor 810 having a memory management unit(MMU) 820 that controls data flows into and out of the processor. Anapplication specific integrated circuit (ASIC) 830 occupies an expansionslot and communicates to a FLASH component 840 and a DRAM buffer 850. Asshown, one or more other slots 860 and 870 can be provided. In general,the processor 810 supports traditional DRAM data flows and timing, wherein order to employ the FLASH component 840, the ASIC 830 providescontrolled access to the FLASH component. Control includes read andwrite timing to the FLASH component 840 along with consideration of wearleveling to any particular sector of the FLASH. The DRAM buffer 850allows temporary high speed access while background operations or otherprocesses may be employed to transfer contents of the buffer to FLASH.The buffer can also be used for a temporary copy area to allow one areaof FLASH to be re-mapped to another location of FLASH to mitigate wearin a given memory location.

In general, the processor 810 can communicate with each of the expansionslots 830, 860, and 870, where each slot can communicate with two ormore channels. The ASIC 830 employs one channel (or more) to communicatewith the FLASH component 840 and another channel (or more) tocommunicate with the DRAM buffer 850. As data from an application iswritten into the temporary DRAM buffer 850, it can be moved to the FLASH840 during background operations or in accordance with other proceduresdescribed in more detail below. In an alternative aspect, an operatingsystem (not shown) can be modified to recognize the FLASH component840/DRAM Buffer 850 and thus employ the MMU 820 to update the FLASH fromthe DRAM buffer. The ASIC 830 basically controls or provides acontrolled access in accordance with timing of the FLASH component 840.As can be appreciated, the expansion slots can be employed in variousaspects. This include providing additional ASIC/memory expansion,providing additional FLASH capability of adding additional buffermemory. Memory can be configured as a dual inline memory module (DIMM)for the ASIC, FLASH, and/or DRAM buffer respectively. Thus, theexpansion slots can be used to provide more ASIC capabilities, moreFLASH capabilities, and/or more DRAM buffer capability. It is to beappreciated that dual in line memory module configurations are but oneof many possible configurations and that substantially any type ofpackaging arrangement for FLASH and/or DRAM are possible.

The system 800 can include one or more memory components that can becomprised of a non-volatile memory (e.g., FLASH memory) and/or volatilememory (e.g., random access memory (RAM)). The memory components canreceive information, including data, commands, and/or other information,which can be processed (e.g., store data, execute commands, etc.). Thememory components can include a memory array that can receive and storedata. The memory array can include a plurality of memory cells whereineach memory cell can store one or more bits of data. Data stored in amemory cell(s) in the memory array can be read and such data can beprovided as an output, or can be erased from the memory cell(s) inaccordance with the timing and wear considerations of the FLASHcomponent 840.

Conventionally, when data is desired from a memory (e.g., FLASH memory),a host processor 830 can issue a command to the memory, where the memorycommand can include information regarding the particular memory deviceand a particular block, where the data can be stored on a page withinthe block. The memory can load a page from that block into a buffer(e.g., page buffer), where typically there can be multiple loads inorder to load the page. In one aspect, the memory array can be comprisedof a predetermined number of blocks, where a block can be the minimumportion of the memory component (e.g., FLASH memory) that can be erasedand programmed during an erase operation.

Turning to FIG. 9, a system 900 illustrates wear leveling concepts forFLASH memory devices. In this aspect, consideration is given to theconcept that FLASH devices can wear out over time if the same memoryaddresses are always employed. Conventionally, FLASH memories weremanaged similar to a disk where a file system for memory management isused. The operating system communicates with the file system whichinforms about deleting or adding of files to the memory. The file systemis aware of unmapped or free sectors within FLASH memory. When wearleveling is applied, a frequently written sector is de-mapped andreplaced by an infrequently written sector. From the free sector pool.For a completely full memory, this process can be entirely inefficientin that swapping of sectors can take up to two program writes andcorresponding erase procedures.

The system 900 illustrates different operations to perform wear levelingin a FLASH based random access system. As shown, a memory manager 910communicates with a FLASH memory 920. An additional DRAM buffer 930 isprovided that is not visible to the main memory/operating systemarchitecture. The DRAM buffer 930 is employed as a temporary storagearea to allow re-mapping of lightly used FLASH addresses with moreheavily used areas of FLASH. Thus, the DRAM buffer is only visibly tothe memory manager 910 and employed as a data exchange area for areas ofFLASH memory that are heavily used. The spare capacity provided by theDRAM buffer 930 provides sector swap capabilities to facilitate wearleveling across the FLASH 920. In an alternative aspect, operatingsystem software can be modified to provide a free list component 940.The operating system can inform an ASIC or other controller of areas ofrandom access memory that are considered free and not currently in useby one or more applications. Such free list areas can be employed inlieu of the DRAM buffer 930 for wear leveling. As can be appreciated, acombination of DRAM buffer 930 and the free list component 940 couldalso be employed to perform wear leveling. It is noted that variouscounters can be maintained to track what sectors have been used and todetermine when to perform wear leveling in the system e.g., thresholdcounter levels to determine when to swap highly used sectors withlightly used ones.

Referring now to FIG. 10, a system 1000 illustrates write timing access.As shown, write data 1010 is controlled by a memory manager 1020. Thewrite data can be captured by a DRAM buffer 1030 and subsequently movedto a FLASH memory 1040 over time such as background operations of aprocess or thread. By moving the write data 1010 over time, the slowerwrite times for the FLASH can be accommodated. In general, the DRAMbuffer 1030 can be sized differently depending on applicationconsiderations. In one aspect, at 1050, the DRAM 1030 is sized such thatit can temporarily hold data for any working set of a given application.In another aspect at 1060, if the change rate of the write working setto the DRAM buffer 1030 is slower than the update rates to the FLASH1040, then even though the application can demand a much higherbandwidth than the FLASH can offer, such application can still executeefficiently on the system.

In yet another aspect, bursting behavior is considered at 1070. Here,data to be written may not change all that often but when data iswritten, it is written at a high rate over a short period of time. Inthis case, the DRAM 1030 can be employed to capture the high data rateand use background operations to spread that rate out over time. Inother cases, operating system behavior can be modified to mitigatebursts such that data that is updated infrequently can be written over alonger period of time. Generally, data is written to the FLASH in chunksof sectors. Thus, typically at least one sector is cached in the DRAMbefore subsequently updating the FLASH.

Referring now to FIG. 11, read and write bandwidth consideration issuesare discussed for FLASH memory updates. As discussed above, write data1110 to a FLASH 1120 is typically controlled by an ASIC performing amemory manager function 1130 that controls timing to the FLASH. In orderto mitigate system bandwidth from slowing down (e.g., copying from FLASHto buffer and vise versa), it is also desirable to mitigate how oftencontents of the FLASH 1120 are copied into a temporary DRAM storage area1140. In conventional architectures, it is typical to copy all thecontents for an application into working memory such as paging in from adisk. In this case, a partial allocation function 1150 is written wherea small section of the FLASH 1120 is copied into the DRAM 1140 andupdated with the corresponding write data 1110 from the application. Ifthe application needs to read data, the small sector that has beenupdated can be read from the DRAM 1140 and the rest of the applicationdata that was not copied can be read from FLASH.

Overtime or after the page is no longer used, the updated write contentsof the DRAM can be transferred into the FLASH 1120 as previouslydescribed above. The partial allocate function 1150 operates overincoming write requests that are written to DRAM pages. Othernon-modified data is not brought into the DRAM from the FLASH 1120 thusconserving the number of read and write cycles on the system bus. Themodified page can stay in DRAM 1140 as long as needed.

Referring to FIG. 12, a block diagram illustrates an exemplary,non-limiting electronic device 1200 that can comprise and/or incorporatethe systems or components previously described. The electronic device1200 can include, but is not limited to, a computer, a laptop computer,network equipment (e.g., routers, access points), a media player and/orrecorder (e.g., audio player and/or recorder, video player and/orrecorder), a television, a smart card, a phone, a cellular phone, asmart phone, an electronic organizer, a PDA, a portable email reader, adigital camera, an electronic game (e.g., video game), an electronicdevice associated with digital rights management, a Personal ComputerMemory Card International Association (PCMCIA) card, a trusted platformmodule (TPM), a Hardware Security Module (HSM), set-top boxes, a digitalvideo recorder, a gaming console, a navigation system or device (e.g.,global position satellite (GPS) system), a secure memory device withcomputational capabilities, a device with a tamper-resistant chip(s), anelectronic device associated with an industrial control system, anembedded computer in a machine (e.g., an airplane, a copier, a motorvehicle, a microwave oven), and the like.

Components of the electronic device 1200 can include, but are notlimited to, a processor component 1202 (e.g., which can be and/or caninclude the same or similar functionality as processor component 302, asdepicted in FIG. 3 and described herein), a system memory 1204, whichcan contain a nonvolatile memory 1206, and a system bus 1208 that cancouple various system components including the system memory 1204 to theprocessor component 1202. The system bus 1208 can be any of severaltypes of bus structures including a memory bus or memory controller, aperipheral bus, or a local bus using any of a variety of busarchitectures.

Electronic device 1200 can typically include a variety of computerreadable media. Computer readable media can be any available media thatcan be accessed by the electronic device 1200. By way of example, andnot limitation, computer readable media can comprise computer storagemedia and communication media. Computer storage media includes volatileand non-volatile, removable and non-removable media implemented in anymethod or technology for storage of information such as computerreadable instructions, data structures, program modules or other data.Computer storage media includes, but is not limited to, RAM, ROM,EEPROM, nonvolatile memory 1206 (e.g., FLASH memory), or other memorytechnology, CD-ROM, digital versatile disks (DVD) or other optical diskstorage, magnetic cassettes, magnetic tape, magnetic disk storage orother magnetic storage devices, or any other medium which can be used tostore the desired information and which can be accessed by electronicdevice 1200. Communication media typically embodies computer readableinstructions, data structures, program modules or other data in amodulated data signal such as a carrier wave or other transportmechanism and includes any information delivery media.

The system memory 1204 can include computer storage media in the form ofvolatile (e.g., SRAM) and/or nonvolatile memory 1206 (e.g., FLASHmemory). For example, nonvolatile memory 1206 can be the same orsimilar, or can contain the same or similar functionality, as memorycomponent 1202. A basic input/output system (BIOS), containing the basicroutines that can facilitate transferring information between elementswithin electronic device 1200, such as during start-up, can be stored inthe system memory 1204. The system memory 1204 typically also cancontain data and/or program modules that can be accessible to and/orpresently be operated on by the processor component 1202. By way ofexample, and not limitation, the system memory 1204 can also include anoperating system(s), application programs, other program modules, andprogram data.

The nonvolatile memory 1206 can be removable or non-removable. Forexample, the nonvolatile memory 1206 can be in the form of a removablememory card or a USB FLASH drive. In accordance with one aspect, thenonvolatile memory 1206 can include FLASH memory (e.g., single-bit FLASHmemory, multi-bit FLASH memory), ROM, PROM, EPROM, EEPROM, or NVRAM(e.g., FeRAM), or a combination thereof, for example. Further, a FLASHmemory can comprise NOR FLASH memory and/or NAND FLASH memory. Inaccordance with another aspect, the nonvolatile memory 1206 can compriseone or more memory components.

A user can enter commands and information into the electronic device1100 through input devices (not shown) such as a keypad, microphone,tablet, or touch screen although other input devices can also beutilized. These and other input devices can be connected to theprocessor component 1202 through input interface component 1210 that canbe connected to the system bus 1208. Other interface and bus structures,such as a parallel port, game port or a universal serial bus (USB) canalso be utilized. A graphics subsystem (not shown) can also be connectedto the system bus 1208. A display device (not shown) can be alsoconnected to the system bus 1208 via an interface, such as outputinterface component 1212, which can in turn communicate with videomemory. In addition to a display, the electronic device 1200 can alsoinclude other peripheral output devices such as speakers (not shown),which can be connected through output interface component 1212.

It is to be understood and appreciated that the computer-implementedprograms and software can be implemented within a standard computerarchitecture. While some aspects of the disclosure have been describedabove in the general context of computer-executable instructions thatcan be run on one or more computers, those skilled in the art willrecognize that the technology also can be implemented in combinationwith other program modules and/or as a combination of hardware andsoftware.

Generally, program modules include routines, programs, components, datastructures, etc., that perform particular tasks or implement particularabstract data types. Moreover, those skilled in the art will appreciatethat the inventive methods can be practiced with other computer systemconfigurations, including single-processor or multiprocessor computersystems, minicomputers, mainframe computers, as well as personalcomputers, hand-held computing devices (e.g., PDA, phone),microprocessor-based or programmable consumer electronics, and the like,each of which can be operatively coupled to one or more associateddevices.

The illustrated aspects of the disclosure may also be practiced indistributed computing environments where certain tasks are performed byremote processing devices that are linked through a communicationsnetwork. In a distributed computing environment, program modules can belocated in both local and remote memory storage devices.

It is also to be understood and appreciated that cryptographic protocolscan be employed to facilitate security of data associated with a memory(e.g., memory component 102) in accordance with the disclosed subjectmatter. For example, a cryptographic component (e.g., cryptographicengine) can be employed and can facilitate encrypting and/or decryptingdata to facilitate securing data being written to, stored in, and/orread from the memory. The cryptographic component can provide symmetriccryptographic tools and accelerators (e.g., Twofish, Blowfish, AES,TDES, IDEA, CAST5, RC4, etc.) to facilitate data security. Thecryptographic component can also provide asymmetric cryptographicaccelerators and tools (e.g., RSA, Digital Signature Standard (DSS), andthe like) to facilitate securing data. Additionally, the cryptographiccomponent can provide accelerators and tools (e.g., Secure HashAlgorithm (SHA) and its variants such as, for example, SHA-0, SHA-1,SHA-224, SHA-256, SHA-384, and SHA-512) to facilitate data security.

It is to be appreciated and understood that authentication protocols canbe employed to facilitate security of data associated with the memory(e.g., memory component 102) in accordance with the disclosed subjectmatter. For example, an authentication component can solicitauthentication data from an entity, and, upon the authentication data sosolicited, can be employed, individually and/or in conjunction withinformation acquired and ascertained as a result of biometric modalitiesemployed, to facilitate control access to the memory. The authenticationdata can be in the form of a password (e.g., a sequence of humanlycognizable characters), a pass phrase (e.g., a sequence of alphanumericcharacters that can be similar to a typical password but isconventionally of greater length and contains non-humanly cognizablecharacters in addition to humanly cognizable characters), a pass code(e.g., Personal Identification Number (PIN)), and the like, for example.Additionally and/or alternatively, public key infrastructure (PKI) datacan also be employed by the authentication component. PKI arrangementscan provide for trusted third parties to vet, and affirm, entityidentity through the use of public keys that typically can becertificates issued by the trusted third parties. Such arrangements canenable entities to be authenticated to each other, and to useinformation in certificates (e.g., public keys) and private keys,session keys, Traffic Encryption Keys (TEKs),cryptographic-system-specific keys, and/or other keys, to encrypt anddecrypt messages communicated between entities.

The authentication component can implement one or moremachine-implemented techniques to identify an entity by its uniquephysical and behavioral characteristics and attributes. Biometricmodalities that can be employed can include, for example, facerecognition wherein measurements of key points on an entity's face canprovide a unique pattern that can be associated with the entity, irisrecognition that measures from the outer edge towards the pupil thepatterns associated with the colored part of the eye—the iris—to detectunique features associated with an entity's iris, and finger printidentification that scans the corrugated ridges of skin that arenon-continuous and form a pattern that can provide distinguishingfeatures to identify an entity.

As utilized herein, terms “component,” “system,” “interface,” and thelike, are intended to refer to a computer-related entity, eitherhardware, software (e.g., in execution), and/or firmware. For example, acomponent can be a process running on a processor, a processor, anobject, an executable, a program, and/or a computer. By way ofillustration, both an application running on a server and the server canbe a component. One or more components can reside within a process and acomponent can be localized on one computer and/or distributed betweentwo or more computers.

Furthermore, the disclosed subject matter may be implemented as amethod, apparatus, or article of manufacture using standard programmingand/or engineering techniques to produce software, firmware, hardware,or any combination thereof to control a computer to implement thedisclosed subject matter. The term “article of manufacture” as usedherein is intended to encompass a computer program accessible from anycomputer-readable device, carrier, or media. For example, computerreadable media can include but are not limited to magnetic storagedevices (e.g., hard disk, floppy disk, magnetic strips . . . ), opticaldisks (e.g., compact disk (CD), digital versatile disk (DVD) . . . ),smart cards, and FLASH memory devices (e.g., card, stick, key drive . .. ). Additionally it should be appreciated that a carrier wave can beemployed to carry computer-readable electronic data such as those usedin transmitting and receiving electronic mail or in accessing a networksuch as the Internet or a local area network (LAN). Of course, thoseskilled in the art will recognize many modifications may be made to thisconfiguration without departing from the scope or spirit of thedisclosed subject matter.

Some portions of the detailed description have been presented in termsof algorithms and/or symbolic representations of operations on data bitswithin a computer memory. These algorithmic descriptions and/orrepresentations are the means employed by those cognizant in the art tomost effectively convey the substance of their work to others equallyskilled. An algorithm is here, generally, conceived to be aself-consistent sequence of acts leading to a desired result. The actsare those requiring physical manipulations of physical quantities.Typically, though not necessarily, these quantities take the form ofelectrical and/or magnetic signals capable of being stored, transferred,combined, compared, and/or otherwise manipulated.

It has proven convenient at times, principally for reasons of commonusage, to refer to these signals as bits, values, elements, symbols,characters, terms, numbers, or the like. It should be borne in mind,however, that all of these and similar terms are to be associated withthe appropriate physical quantities and are merely convenient labelsapplied to these quantities. Unless specifically stated otherwise asapparent from the foregoing discussion, it is appreciated thatthroughout the disclosed subject matter, discussions utilizing termssuch as processing, computing, calculating, determining, and/ordisplaying, and the like, refer to the action and processes of computersystems, and/or similar consumer and/or industrial electronic devicesand/or machines, that manipulate and/or transform data represented asphysical (electrical and/or electronic) quantities within the computer'sand/or machine's registers and memories into other data similarlyrepresented as physical quantities within the machine and/or computersystem memories or registers or other such information storage,transmission and/or display devices.

What has been described above includes examples of aspects of thedisclosed subject matter. It is, of course, not possible to describeevery conceivable combination of components or methodologies forpurposes of describing the disclosed subject matter, but one of ordinaryskill in the art may recognize that many further combinations andpermutations of the disclosed subject matter are possible. Accordingly,the disclosed subject matter is intended to embrace all suchalterations, modifications and variations that fall within the spiritand scope of the appended claims. Furthermore, to the extent that theterms “includes,” “has,” or “having,” or variations thereof, are used ineither the detailed description or the claims, such terms are intendedto be inclusive in a manner similar to the term “comprising” as“comprising” is interpreted when employed as a transitional word in aclaim.

What is claimed is:
 1. A system, comprising: a memory that has storedthereon computer-executable components; and a processor that executesthe following computer-executable components stored in the memory: anallocation component that allocates a page from a main storage device toa page buffer and allocates a buffer page for a write referenceassociated with a cache hit in response to a write major page fault,wherein the allocation component determines whether a particular page isallocated to the page buffer in response to a minor page fault; and amanagement component that generates a mapping to the particular page inresponse to a determination that the particular page is allocated to thepage buffer, wherein another page is allocated to a buffer component andthe particular page is demapped in response to a determination that theparticular page is not allocated to the page buffer.
 2. The system ofclaim 1, wherein the allocation component allocates pages to at leastone of a memory device or the page buffer based on a type of page fault.3. The system of claim 1, wherein the allocation component allocates apage associated with defined protection from the main storage device toa memory device in response to a read major page fault.
 4. The system ofclaim 1, further comprising an address match component that compares aplurality of incoming addresses and determines whether a data return isdirected to the page buffer or a memory device based on a program-erasecycle of the memory device.
 5. The system of claim 1, further comprisinga kernel component that detects when the page is fetched from one ormore memory devices.
 6. The system of claim 5, wherein the buffercomponent temporarily stores the page while the page is being stored onthe one or more memory devices.
 7. The system of claim 5, furthercomprising a read or write detection component that facilitates accessto the one or more memory devices.
 8. The system of claim 7, wherein theread or write detection component allocates pages to the one or morememory devices in response to a determination that a read is detected.9. The system of claim 8, wherein the read or write detection componentsets a copy-on-write flag in response to a determination that the readis detected.
 10. The system of claim 8, wherein the read or writedetection component allocates a DRAM page in response to a determinationthat a write is detected.
 11. A method, comprising: allocating a pagefrom a main storage device to a buffer device and allocating a bufferpage for a write reference associated with a cache hit in response to awrite major page fault; determining whether an existing page isallocated to the buffer device in response to a minor page fault;generating a mapping to the existing page in response to the existingpage being allocated to the buffer device; and allocating another pageto the buffer device and demapping the existing page in response to theexisting page not being allocated to the buffer device.
 12. The methodof claim 11, further comprising allocating a page marked with a definedprotection from the main storage device to a memory device in responseto a read major page fault.
 13. The method of claim 11, furthercomprising adapting a kernel component to employ one or more memorydevices and one or more other memory devices as program memory for acomputer.
 14. The method of claim 13, further comprising triggering atleast one update to the one or more memory devices and the one or moreother memory devices based on the write major page fault and the minorpage fault.
 15. The method of claim 14, further comprising directing acontroller to interleave the at least one update among the one or morememory devices and the one or more other memory devices.
 16. The methodof claim 11, further comprising allocating a FLASH device in response toa read operation or allocating a DRAM page in response to a writeoperation.
 17. A non-transitory computer-readable storage mediumcomprising computer-readable instructions that, in response toexecution, cause a computing system to perform operations, comprising:allocating a page from a storage device to a buffer and allocating abuffer page for a write reference associated with a cache hit inresponse to a write major page fault; determining whether an particularpage is allocated to the buffer in response to a minor page fault;establishing a mapping to the particular page in response to theparticular page being allocated to the buffer; and allocating anotherpage to the buffer and demapping the particular page in response to theparticular page not being allocated to the buffer.
 18. Thenon-transitory computer-readable storage medium of claim 17, furthercomprising allocating a page associated with write protection from thestorage device to a memory device in response to a read major pagefault.
 19. The non-transitory computer-readable storage medium of claim17, further comprising differentiating allocation of pages based in parton whether a fault is a major fault or a minor fault.
 20. Thenon-transitory computer-readable storage medium of claim 17, furthercomprising allocating pages to a memory and the buffer based in part ona detected read operation or a detected write operation.